Integrated circuits (also referred to as chips or die) typically comprise a silicon substrate and active semiconductor devices, such as transistors and diodes, and passive components, such as capacitors and resistors, formed from doped regions within the substrate. Passive components can also be formed in material layers overlying the substrate, e.g., polysilicon resistors formed in a polysilicon layer overlying the silicon substrate.
Interconnect structures, also formed in layers overlying the semiconductor substrate, electrically connect the doped regions and the passive components to form a functional integrated circuit. The interconnect structures comprise a plurality of stacked substantially horizontal conductive layers comprising conductive metal interconnect lines (referred to as metal layers) substantially parallel to an upper surface of the substrate. Two successive horizontal conductive layers are separated by a dielectric material layer. Vertical conductive plugs or vias formed in windows or openings of each dielectric layer connect the metal interconnect lines in an overlying and an underlying conductive layer. A topmost conductive layer (i.e., a top metallization layer) comprises conductive bond pads for receiving conductive elements (e.g., bond wires) for connecting the integrated circuit to externally-directed pins or leads of a package. The package also provides mechanical and environmental protection for the integrated circuit.
The process of forming the interconnect structures, referred to as metallization, includes deposition, photolithographic masking and patterning steps, and etching processes. The metal interconnect lines are formed by depositing a layer of conductive material over a dielectric layer and etching the conductive material according to a pattern formed therein during a photolithographic masking step. The openings in the dielectric layer for receiving the conductive plugs or vias are formed by an etch process that creates the openings according to a resist pattern formed on the dielectric layer according to a photolithographic mask. Conductive material is then deposited in the openings to form the conductive vias.
Integrated circuit fabrication comprises a plurality of depositing, doping, masking, patterning and material etching steps applied to a silicon substrate and material layers formed thereover. Certain of these steps utilize a photolithographic mask to define substrate regions that are to undergo subsequent processing steps, while complementary substrate regions are shielded from these processing steps. The mask comprises a stencil-like plate carrying a pattern of the regions to be processed. Light passing through pattern openings exposes a photosensitive resist material deposited on the substrate surface, changing the structure and properties of the resist and rendering the exposed regions soluble in a rinsing solution. After the exposed resist regions have been removed, processing is carried out on the exposed regions, while the unexposed resist regions shield the underlying material layers from the effects of these processing steps. The above exemplary patterning procedure employs a negative-acting resist. Those skilled in the art recognize that a similar pattering process can be carried out using a positive reacting resist and a mask that is complementary to a negative resist mask.
The sequence of processes for forming transistors, resistors, capacitors and other devices of the integrated circuit, including the interconnects, is referred to as a process flow. Once standardized, it is scaled up to manufacture a larger number of wafers. One element of integrated circuit design is to customize the process flow by creating masks to place and connect specific circuits.
An example of a typical circuit design work flow is illustrated in FIG. 1. During a design step 2, the designers prepare a circuit schematic and generate photomasks for the fabrication facility to use in a process flow for fabricating integrated circuits on a wafer lot. Generally, the process flow is divided into a front-end-of-line (FEOL), primarily comprising the process steps before dielectric deposition and metallization, and the back-end-of-line (BEOL), comprising the remaining steps, including metallization.
After a wafer lot is processed through an FEOL step 3, some of the wafers are split from the lot and held for later processing, as indicated at a step 4. The remaining wafers are processed through the BEOL at a step 5. The processed wafers are tested at a step 6 to ensure that the circuits formed thereon satisfy the applicable specifications. If not, the design is refined at a step 7 during which new masks are generated to reflect the new design. Often, these mask changes affect only BEOL masks, in which case the set aside wafer lot is processed through the redesigned BEOL at a step 8 using the new masks. The set-aside wafers are tested at a step 9. The original circuit design may include provisions to accommodate design changes after testing, such that the changes require modifications to the BEOL masks only.
As is known in the art, the processes employed to design and fabricate each mask are time intensive and expensive. All integrated circuit fabricators expend considerable effort to limit the number of masking steps in the fabrication process flow and to avoid mask changes. As with any fabrication or manufacturing process, it is obvious that integrated circuit redesign time and costs must be minimized.
One specific aspect of circuit redesign involves changing resistor values. In one prior art approach, an integrated circuit includes a plurality of spare resistors having different values. If it is required to change a resistor value, the interconnect structures are adjusted (by using a redesigned mask) to connect a different resistor, selected from among the spare resistors, in place of the resistor used in the original design. Series and parallel combinations of the spare resistors can also be formed to produce a composite resistor having the desired resistance. These series and parallel combinations are also created by modifying the interconnect structures and the masks used to create those structures.
Disadvantageously, a range of available resistances may be limited as in practice the number of spare resistors of different resistance values that can be readily and practically fabricated in the integrated circuit is relatively small. Also, it may be difficult to modify the interconnect structures to accommodate a different resistor, and further the modification may involve changing interconnect structures on multiple interconnect levels. Thus inserting a different resistor into the circuit may require layout-intensive changes that consume considerable time and risk introducing errors into the integrated circuit.
According to another prior art approach, a resistor value is modified by adjusting a length or a width of material from which the resistor is formed according to an original mask. For example, a resistor formed from a polysilicon bar having a length of 10 microns and a width of 1.6 microns presents a certain resistance value based on the dimensions and properties of the polysilicon material disposed between a first and a second resistor contact. The resistance can be adjusted, as required by circuit design modifications, to a lower value by reducing the length of the polysilicon material disposed between the two contacts (e.g., to 8 microns), which is accomplished by relocating at least one of the contacts. Conversely, the resistance can be modified to a higher value by moving the contacts farther apart, i.e., by moving at least one of the contacts.
Either of these resistance changes to increase or decrease the resistance requires at least three mask changes. The mask used to form the polysilicon material must be modified to form either a longer or a shorter polysilicon bar. The resistor contacts are formed according to patterned openings in a material layer overlying the polysilicon bar. Since in both cases at least one of the contacts is relocated, a second mask change is required to realize contact relocation. Finally, at its upper end, each contact is in electrical communication with an overlying interconnect layer (i.e., a conductive line) to electrically connect the contact, and thus the resistor, into a circuit of the integrated circuit. Since at least one contact is relocated, it is necessary to modify the mask for forming the overlying interconnect lines to contact the contacts at the new location. Thus three mask changes are required to change a single resistance value. Also, integrated circuit resistors are typically placed in arrays with a minimum required resistor spacing or a minimum distance to adjacent circuit elements. Increasing the length or width of the resistive material may require changes to several layers and thus several masks, in addition to the mask used for forming the material.
After the new masks are designed, wafers are processed using the new mask set. But since these mask change may involve one or more FEOL masks (e.g., the mask for forming the polysilicon bar), use of the staged wafers as depicted in FIG. 1 does not save process flow cycle time, and a new wafer lot must be processed to implement the resistance changes.